PARALLEL SIMULATED ANNEALING - ACCURACY VS SPEED IN PLACEMENT

被引：9

作者：

DURAND, MD

机构：

[1] Durand, M.Dannie

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1989年 / 6卷 / 03期

关键词：

Computer Systems; Digital - Parallel Processing - Integrated Circuits - Computer Aided Design - Mathematical Techniques - Combinatorial Mathematics - Systems Science and Cybernetics - Heuristic Programming;

D O I：

10.1109/54.32410

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Techniques researchers have used to control error in VLSI placement are surveyed. The discussion covers: the application of parallelism, synchronization with serial subsets, combining algorithms, periodic synchronization, shared-memory implementation, local-memory implementation, and Connection Machine implementation. The issues of temporary versus cumulative error, task allocation, and error measurements are examined.

引用

页码：8 / 34

页数：27

共 22 条

[1]

BANNERJEE P, 1986, P IEEE INT C COMPUTE, P34

[2]

BREUER MA, 1977, J DES AUTOM FAULT, V1, P343

[3] A PARALLEL SIMULATED ANNEALING ALGORITHM FOR THE PLACEMENT OF MACROCELLS [J].

CASOTTO, A ;

ROMEO, F ;

SANGIOVANNIVINCENTELLI, A .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (05) :838-847

[4]

CASOTTO A, 1987, NOV P INT C COMP AID, P350

[5]

Casotto A., 1986, P IEEE INT C COMP AI, P30

[6]

DAREMA F, 1987, IEEE DESIGN TEST OCT, P19

[7]

DAREMARODGERS F, 1985, RC11225 IBM TECH RPT

[8]

DAREMAROGERS F, 1986, RC12195 IBM TECH RPT

[9]

GROVER L, 1987, SIMULATED ANNEALING

[10]

Hillis W. D., 1985, THESIS MASSACHUSETTS

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