SCHEDULING FOR IC SORT AND TEST WITH PREEMPTIVENESS VIA LAGRANGIAN-RELAXATION

被引:28
作者
CHEN, TR [1 ]
CHANG, TS [1 ]
CHEN, CW [1 ]
KAO, J [1 ]
机构
[1] VLSI TECHNOL INC,SAN JOSE,CA 95131
来源
IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS | 1995年 / 25卷 / 08期
关键词
D O I
10.1109/21.398686
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a Lagrangian relaxation approach for the scheduling problem of an IC sort and test facility. In an Integrated Circuit (IC) manufacturing environment, a combination of tester, prober, and some hardware facilities is needed for wafer sort while a combination of tester, handler, and some other hardware facilities is needed for final test. To schedule both sorting and testing at the same time, the resource constraints on testers, probers, handlers and hardware have to be dealt with. This paper also extends the Lagrangian relaxation technique to solve a class of preemptive scheduling problems which particularly exist in an IC test floor environment. Numerical examples are given to illustrate the potential of our approach. Comparisons of our results with those obtained by some heuristic rules are also given.
引用
收藏
页码:1249 / 1256
页数:8
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