POWER-SUPPLY VOLTAGE IMPACT ON CIRCUIT PERFORMANCE FOR HALF AND LOWER SUBMICROMETER CMOS LSI

Power-supply voltage effects on circuit performance, taking into account high electric field effects on a MOSFET, have been theoretically and experimentally examined in detail for CMOS devices down to half and lower submicrometer gate length. Based upon theoretical understanding, the authors introduce the concept that the lower power supply voltage limit can be simply expressed by 1.1 Ec, Leff, where Ec is the critical electric field necessary to cause carrier velocity saturation and Leff is the effective channel length. Experimental results confirmed that 1.1EcLeff predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3–2.0 µm). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling have been demonstrated. Moreover, it has been clarified that 1.1Ec Leff can be regard as lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6-µm channel length at reduced power supply. Finally, transconductance behavior for MOSFET under high electric fields was investigated in order to explain physical meaning of 1.1Ec Leff. © 1990 IEEE