CCD FOCAL-PLANE IMAGE REORGANIZATION PROCESSORS FOR LOSSLESS IMAGE COMPRESSION

Four image reorganization IC's to enable real-time difference encoding for hierarchical lossless image compression are reported. Two image reorganization processors are realized on the focal plane and two were designed for hybridization to a separate imager IC. The two focal-plane IC's represent the first integration of a 256 X 256 buried-channel frame-transfer CCD image sensor with additional charge-domain circuitry to enable image reformatting at video rates (28 frames/s). The reformatting circuitry occupies 2% of the IC area with an estimated power dissipation of less than 150-mu-W at a 30-Hz frame rate. The four IC's generate pyramidal pixel output in 3 x 3 blocks with the center pixel first. Pixel data reorganization is performed through simultaneous readout of three rows of data, followed by pixel resequencing and sampling to provide differential output. A novel architecture, consisting of three parallel-serial-parallel registers (Sp3) provides simultaneous readout of multiple imager rows on the focal-plane IC's. The IC's have achieved a charge-transfer efficiency (CTE) of 0.99996 in the conventional horizontal and vertical CCD registers, and a CTE of 0.99994 in the SP3 registers. The overall output amplifier sensitivity is 3.2-mu-V/electron.