AN ANALOG NEURAL NETWORK PROCESSOR WITH PROGRAMMABLE TOPOLOGY

被引:85
作者
BOSER, BE
SACKINGER, E
BROMLEY, J
LECUN, Y
JACKEL, LD
机构
[1] AT&T Bell Laboratories, Holmel, NJ
关键词
D O I
10.1109/4.104196
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The architecture, implementation, and applications of a special-purpose neural network processor are described. The chip performs over 2000 multiplications and additions simultaneously. Its data path is particularly suitable for the convolutional topologies that are typical in classification networks, but can also be configured for fully connected or feed-back topologies. Resources can be multiplexed to permit implementation of networks with several hundreds of thousands of connections on a single chip. Computations are performed with 6-b accuracy for the weights and 3 b for the neuron states. Analog processing is used internally for reduced power dissipation and higher density, but all input/output is digital to simplify system integration. The practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition. This network contains over 130 000 connections and is evaluated in 1 ms.
引用
收藏
页码:2017 / 2025
页数:9
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