A 15-NS 16-MB CMOS SRAM WITH INTERDIGITATED BIT-LINE ARCHITECTURE

This paper describes circuit techniques for a reduced-voltage-amplitude data bus, fast access 16-Mb CMOS SRAM. An interdigitated bit-line architecture reduces data bus line length, thus minimizing bus capacitance. A hierarchical sense amplifier consists of 32 local sense amplifiers and a current sense amplifier. The current sense amplifier is used to reduce the data bus voltage amplitude and the sensing of the 16-b data bus signals in parallel. With these techniques we achieved a fast access time of 15 ns and a small active power of 165 mW in a 16-Mb CMOS SRAM. A split-word-line layout memory cell, with double-gate pMOS thin-film transistors (TFT's), keeps the transistor width stable while providing high-stability memory cell characteristics. The double-gate pMOS TFT also increases cell-storage node capacitance and soft-error immunity.