AN ALL-DIGITAL PHASE-LOCKED LOOP WITH 50-CYCLE LOCK TIME SUITABLE FOR HIGH-PERFORMANCE MICROPROCESSORS

被引：135

作者：

DUNNING, J

GARCIA, G

LUNDBERG, J

NUCKOLLS, E

机构：

[1] Motorola, Inc., Austin

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1995年 / 30卷 / 04期

关键词：

Phase locked loops;

D O I：

10.1109/4.375961

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 mu m CMOS microprocessor, The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter, A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4x the reference clock frequency, The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.

引用

页码：412 / 422

页数：11