DESIGN OF A LOW-POWER 32K CMOS PROGRAMMABLE DELAY-LINE MEMORY

被引：1

作者：

DEJHAN, K

DEMASSIEUX, N

COLAVIN, O

GALISSON, A

ARTIERI, A

JUTAND, F

机构：

[1] Ecole National Supérieure des Télécommunications (ENST)

[2] Ecole National Superieure des Telecommunications (ENST)

[3] SGS-Thomson

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 01期

关键词：

D O I：

10.1109/4.50309

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

- A design of a programmable digital delay line based on shift registers in 1.2-μm CMOS technology is presented. The main features of this design are 20-MHz operating frequency and 200-mW power dissipation for four 1024-pixel × 8-bit delay lines.1 An integrable circuit technique for decreasing the power dissipation of the shift register has also been suggested. © 1990 IEEE

引用

页码：234 / 238

页数：5

共 10 条

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[2]

GREBENE A, 1984, BIPOLAR MOS ANALOG I

[3]

Hodges D., 1983, ANAL DESIGN DIGITAL

[4]

JEN TS, 1971, FAL JOINT COMP C, P171