16-MB SYNCHRONOUS DRAM WITH 125-MBYTE/S DATA RATE

被引：6

作者：

CHOI, YH

KIM, MH

JANG, HS

KIM, TJ

LEE, SH

LEE, HC

PARK, CR

LEE, SY

KIM, CS

CHO, SI

HAQ, E

KARP, J

CHIN, DJ

机构：

[1] Product Development Center, Memory Division, Samsung Electronics, Suwon, Kyungki-Do

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1994年 / 29卷 / 04期

关键词：

D O I：

10.1109/4.280704

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M x 8) achieves a 125-Mbyte/s data rate using 0.5-mum twin well CMOS technology.

引用

页码：529 / 533

页数：5