AN EXPERIMENTAL 4-MB FLASH EEPROM WITH SECTOR ERASE

A 512K x 8 flash EEPROM which operates from a single 5-V supply has been designed and fabricated. A double-poly, single-metal CMOS process with a minimum feature size of 0.9-mu-m was developed to manufacture the test vehicle, which resulted in a die size of 95 mm2. The storage cell is 8.64-mu-m2 and consists of a one-transistor cell that uses a remote, scalable, tunnel diode for programming and erasing by Fowler-Nordheim tunneling. Process high-voltage requirements are relaxed by utilizing circuit techniques to operate the device at less process extremes. A segmented architecture provides the flexibility to erase any one sector (16 kilobytes) or the entire chip during one cycle by an erase algorithm. The memory may be programmed 1 byte at a time, or the internal bit-line latches may be used to program a 256-byte page in one cycle. A programming time of 10 ms is typical, which results in a write time of 40-mu-s/byte during page programming. The chip features an access time of 90 ns.