CONSTANT-G(M) RAIL-TO-RAIL COMMON-MODE RANGE INPUT STAGE WITH MINIMUM CMRR DEGRADATION

In this paper the inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated on the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as function of the input common-mode voltage, it provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in regard to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2-mum feature size are given.