LATCH-UP CONTROL IN CMOS INTEGRATED-CIRCUITS

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (~9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. This paper will survey latch-up control methods presently employed for weapons and space applications on present (~9 μm p-well) CMOS and will indicate the extent of their applicability to VLSI designs. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.