OPTIMAL GRANULARITY OF TEST-GENERATION IN A DISTRIBUTED SYSTEM

被引：13

作者：

FUJIWARA, H

INOUE, T

机构：

[1] Department of Computer Science, Meiji University, Kawasaki 214, Tama-ku

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1990年 / 9卷 / 08期

关键词：

Logic Circuits;

D O I：

10.1109/43.57783

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The problem of test generation for logic circuits is known to be NP-hard, and hence, it is very hard to speedup the test generation process due to its backtracking mechanism. This paper presents an approach to parallel processing of test generation for logic circuits in a loosely-coupled distributed network of general purpose computers, and analyzes the effects of the allocation of target faults to processors, the optimal granularity (grain size of target faults), and the speedup ratio of the multiple processor system to a single processor system. © 1990 IEEE

引用

页码：885 / 892

页数：8

共 26 条

[1]

BLANK T, 1984, IEEE DESIGN TEST AUG, P21

[2]

BRGLEZ F, 1985, JUN P IEEE INT S CIR

[3]

CHANDRA SJ, 1988, OCT IEEE INT C COMP, P11

[4]

CVETANOVIC Z, 1987, IEEE T COMPUT, V36, P421, DOI 10.1109/TC.1987.1676924

[5]

Duba P. A., 1988, 25th ACM/IEEE Design Automation Conference. Proceedings 1988 (Cat. No.88CH2540-3), P686, DOI 10.1109/DAC.1988.14843

[6]

ELZIQ YM, 1984, P IEEE INT C COMPUTE, P257

[7]

Fujiwara H., 1988, Transactions of the Institute of Electronics, Information and Communication Engineers E, VE71, P441

[8]

FUJIWARA H, 1983, IEEE T COMPUT, V32, P1137, DOI 10.1109/TC.1983.1676174

[9]

FUJIWARA H, 1982, IEEE T COMPUT, V31, P555, DOI 10.1109/TC.1982.1676041

[10]

GOEL P, 1981, IEEE T COMPUT, V30, P215, DOI 10.1109/TC.1981.1675757

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