SUPERCONDUCTING SAMPLER FOR JOSEPHSON LOGIC-CIRCUITS

被引：23

作者：

HAMILTON, CA

LLOYD, FL

PETERSON, RL

ANDREWS, JR

机构：

[1] Electromagnetic Technology Division, National Bureau of Standards, Boulder

来源：

APPLIED PHYSICS LETTERS | 1979年 / 35卷 / 09期

关键词：

D O I：

10.1063/1.91266

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

A method is described for automating a technique which is used to sample transition duration (rise time) in superconducting logic circuits. The method is based on measuring the time at which a biased Josephson junction switches under the influence of an applied signal. The system transition duration is limited primarily by time jitter which is estimated to be 7 ps. Transition durations of as little as 9 ps have been observed.

引用

页码：718 / 719

页数：2

共 6 条

[1] DELAY MEASUREMENT OF EXPERIMENTAL 2.5-MU-M JOSEPHSON CURRENT INJECTION LOGIC (CIL) [J].