PROGRAMMABLE CCD CORRELATOR

被引：6

作者：

HERRMANN, EP ^{[1
]}

GANDOLFO, DA ^{[1
]}

机构：

[1] RCA,ADV TECHNOL LABS,CAMDEN,NJ 08102

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1979年 / 26卷 / 02期

关键词：

D O I：

10.1109/T-ED.1979.19389

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A programmable CCD tapped delay line, useful in radar and communications signal processors, is described. The 64-stage CCD, tapped at each stage, has been operated as a binary-weighted analog correlator, and as a bandpass filter. The CCD is a shallow, buried, n- channel device while the on-chip logic required for reference code in-put and storage is NMOS. Test results indicate near-theoretical peak-to-sidelobe ratio for 64-bit codes, good linearity, and high-speed operation (in excess of 15 MHz). Differential subtraction of summed signal currents on-chip has been demonstrated. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.

引用

页码：117 / 122

页数：6

共 7 条

[1]

HERRMANN EP, 1976, 3RD INT C TECHN APPL

[2]

KOSONOCKY W, 1976, Patent No. 3986198

[3]

KOSONOCKY WF, 1975, RCA REV, V36, P566

[4] CHARGE-COUPLES DIGITAL CIRCUITS [J].