TWISTED BIT-LINE ARCHITECTURES FOR MULTI-MEGABIT DRAMS

被引:39
作者
HIDAKA, H [1 ]
FUJISHIMA, K [1 ]
MATSUDA, Y [1 ]
ASAKURA, M [1 ]
YOSHIHARA, T [1 ]
机构
[1] MITSUBISHI ELECT CORP,LSI RES & DEV LAB,ITAMI,HYOGO 664,JAPAN
关键词
D O I
10.1109/4.16297
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:21 / 27
页数:7
相关论文
共 8 条
[1]  
Aoki M., 1988, ISSCC DIG TECH PAPER, P250
[2]  
INOUE M, 1988, ISSCC DIG TECH PAPER, P246
[3]  
MANO T, 1987, ISSCC DIG TECH PAPER, P22
[4]   A 5 V-ONLY 64K DYNAMIC RAM BASED ON HIGH S-N DESIGN [J].
MASUDA, H ;
HORI, R ;
KAMIGAKI, Y ;
ITOH, K ;
KAWAMOTO, H ;
KATTO, H .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (05) :846-854
[5]  
SUZUKI S, 1984, ISSCC DIG TECH PAPAE, P106
[6]  
WATANABE S, 1988, ISSCC DIG TECH PAPER, P248
[7]  
YOSHIDA M, 1985, P VLSI S, V6, P6
[8]  
YOSHIHARA T, 1988, ISSCC DIG TECH PAPER, P238