A PIXEL UNIT-CELL TARGETING 16NS RESOLUTION AND RADIATION HARDNESS IN A COLUMN READ-OUT PARTICLE VERTEX DETECTOR

A pixel unit cell (PUC) circuit architecture, optimized for a column read out architecture, is reported. Each PUC contains an integrator, active filter, comparator, and optional analog store. The time-over-threshold (TOT) discriminator allows an all-digital interface to the array periphery readout while passing an analog measure of collected charge. Use of (existing) radiation hard processes, to build a detector bump-bonded to a pixel readout array, is targeted. Here emphasis is on a qualitative explanation of how the unique circuit implementation benefits operation for Super Collider (SSC) detector application.