A PROPOSED SEU TOLERANT DYNAMIC RANDOM-ACCESS MEMORY (DRAM) CELL

A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors; The informational charge packet is shielded from the single event by placing the vulnerable node in a self-compensating state while the cell is in standby mode. The proposed cell is comparable in size to a conventional DRAM cell, and computer simulations show an improvement in critical charge of two orders of magnitude over Conventional 1-T DRAM cells.