HIGH-SPEED SI-BIPOLAR IC DESIGN FOR MULTI-GB/S OPTICAL RECEIVERS

This paper proposes a high-speed Si-bipolar IC design for multi-Gb/s optical receivers. We developed several special circuits to minimize the decrease in speed caused by parasitics. The common-base circuit assures flat and wide frequency preamplifier response even when V(EE) is unstable because of bond wire inductance. Cascode interconnections between circuit blocks prevent waveform degradation due to line capacitance discharge. The high level of integration prevents signal speed from decreasing due to chip interfaces and external interference. Using these circuits and Si-bipolar ESPER (emitter-base self-aligned structure with polysilicon electrodes and resistors) transistors whose j was 28 GHz, we fabricated three IC's: a preamplifier with a 5.1 GHz bandwidth, a fully integrated AGC amplifier with a 3.6 GHz bandwidth, and a decision circuit that operates at 10.6 Gb/s. We used these IC's and an APD to construct a 5 Gb/s optical receiver with a minimum detectable optical power of -26.8 dBm. The speed of the Si IC's exceeded 5 Gb/s.