NOVEL CELL ARCHITECTURE FOR HIGH-PERFORMANCE DIGIT-SERIAL COMPUTATION

被引：12

作者：

AGGOUN, A

ASHUR, A

IBRAHIM, MK

机构：

[1] Electrical and Electrical Engineering Department, University of Nottingham, Nottingham

来源：

ELECTRONICS LETTERS | 1993年 / 29卷 / 11期

关键词：

DIGITAL ARITHMETIC; PIPELINE PROCESSING;

D O I：

10.1049/el:19930625

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new cell architecture for high performance digit-serial computation is presented. The design of this cell is based on the feedforward of the carry digit, which allows a high level of pipelining to increase the throughput rate. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. The effect of the number of pipelining levels on the throughput rate and hardware cost are presented.

引用

页码：938 / 940

页数：3

共 6 条

[1]

HATLEY R, 1990, IEEE T CIRCUITS SYST, V37, P707

[2] PROGRAMMABLE 2D LINEAR FILTER FOR VIDEO APPLICATIONS [J].