THE SP2 HIGH-PERFORMANCE SWITCH

被引：101

作者：

STUNKEL, CB ^{[1
]}

SHEA, DG ^{[1
]}

ABALI, B ^{[1
]}

ATKINS, MG ^{[1
]}

BENDER, CA ^{[1
]}

GRICE, DG ^{[1
]}

HOCHSCHILD, P ^{[1
]}

JOSEPH, DJ ^{[1
]}

NATHANSON, BJ ^{[1
]}

SWETZ, RA ^{[1
]}

STUCKE, RF ^{[1
]}

TSAO, M ^{[1
]}

VARKER, PR ^{[1
]}

机构：

[1] IBM CORP,DIV POWER PARALLEL,HIGHLY PARALLEL SUPERCOMP SYST LAB,POUGHKEEPSIE,NY 12601

来源：

IBM SYSTEMS JOURNAL | 1995年 / 34卷 / 02期

关键词：

D O I：

10.1147/sj.342.0185

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The heart of an IBM Sp2(TM) system is the High-Performance Switch, which is a low-latency, high-bandwidth switching network that binds together RISC System/6000(R) processors. The switch incorporates a unique combination of topology and architectural features to scale aggregate bandwidth, enhance reliability, and simplify cabling. It is a bidirectional multistage interconnect subsystem driven by a common oscillator and delivers both data and service packets over the same links. Switching elements contain a dynamically allocated shared buffer for storing blocked packet flits. The switch is constructed primarily from switching elements (the Vulcan switch chip) and adapters (the SP2 communication adapter). The SP2 communication adapter uses a variety of techniques to improve bandwidth and offload communication tasks from the node processor. This paper examines the switch architecture and presents an overview of its support software.

引用

页码：185 / 204

页数：20

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