OPTIMIZED REDUNDANCY SELECTION BASED ON FAILURE-RELATED YIELD MODEL FOR 64-MB DRAM AND BEYOND

This paper describes an optimized redundancy scheme for 64-Mb DRAM and beyond, based on a failure-related yield model. This model accounts for three-dimensional memory cell structures and individual design rules used in individual sections of the chip. Failure-mode parameters for the model are determined by performing a trial fuse-blowing test on 4-Mb DRAM's, which employs a memory tester without requiring complicated visual inspections. Then, the dependence of the yield on block division and the number of spare elements for a 64-Mb DRAM are investigated. In the estimation, as a redundancy scheme for the 64-Mb DRAM, more than two spare rows and two spare columns in 1-Mb or less subblocks are shown to be necessary.