SINGLE 5-V, 64K RAM WITH SCALED-DOWN MOS STRUCTURE

被引：2

作者：

MASUDA, H

HORI, R

KAMIGAKI, Y

ITOH, K

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1980年 / 15卷 / 04期

关键词：

D O I：

10.1109/JSSC.1980.1051454

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：672 / 677

页数：6

共 11 条

[1]

CENKER R, 1979, ISSCC DIG TECH PAPER, P150

[2] DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].

DENNARD, RH ;

GAENSSLEN, FH ;

YU, HN ;

RIDEOUT, VL ;

BASSOUS, E ;

LEBLANC, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268

[3] FUNDAMENTAL LIMITATIONS IN MICROELECTRONICS .1. MOS TECHNOLOGY [J].

HOENEISEN, B ;

MEAD, CA .

SOLID-STATE ELECTRONICS, 1972, 15 (07) :819-+

[4]

ITOH K, 1980, IEEE ISSCC TECH DIG

[5]

KAMIGAKI Y, 1979, 40TH C APPL PHYS JAP, P457

[6]

LEE I, 1979, ISSCC DIG TECH PAPER, P146

[7] CHARACTERISTICS AND LIMITATION OF SCALED-DOWN MOSFETS DUE TO 2-DIMENSIONAL FIELD-EFFECT [J].

MASUDA, H ;

NAKAI, M ;

KUBO, M .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (06) :980-986

[8] 64 KBIT MOS DYNAMIC RANDOM-ACCESS MEMORY [J].

NATORI, K ;

OGURA, M ;

IWAI, H ;

MAEGUCHI, K ;

TAGUCHI, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (02) :482-485

[9] 1 MU-M MOSFET VLSI TECHNOLOGY .4. HOT-ELECTRON DESIGN CONSTRAINTS [J].

NING, TH ;

COOK, PW ;

DENNARD, RH ;

OSBURN, CM ;

SCHUSTER, SE ;

YU, HN .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (02) :268-275

[10]

SUNAMI H, 1978, 10TH P C SOL STAT DE

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