EPITAXIAL V-GROOVE BIPOLAR INTEGRATED-CIRCUIT PROCESS

被引:20
作者
RODGERS, TJ [1 ]
MEINDL, JD [1 ]
机构
[1] STANFORD UNIV,DEPT ELECT ENGN,STANFORD,CA 94304
关键词
D O I
10.1109/T-ED.1973.17633
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:226 / 232
页数:7
相关论文
共 14 条
[1]  
GHANDI SK, 1968, THEORY PRACTICE MICR, P180
[2]  
HALSOR J, 1969, SOLID STATE TECHNOL, P15
[3]   MATERIAL AND PROCESS CONSIDERATIONS FOR MONOLITHIC LOW-1/F-NOISE TRANSISTORS [J].
KHAJEZAD.H ;
MCCAFFRE.TT .
PROCEEDINGS OF THE IEEE, 1969, 57 (09) :1518-&
[4]   ANISOTROPIC ETCHING OF SILICON [J].
LEE, DB .
JOURNAL OF APPLIED PHYSICS, 1969, 40 (11) :4569-&
[5]  
MALEY GA, 1970, MANUAL LOGIC CIRCUIT, P256
[6]  
MALEY GA, 1970, MANUAL LOGIC CIRCUIT, P255
[7]  
MEYER C, 1968, ANALYSIS DESIGN INTE, P200
[8]   COLLECTOR DIFFUSION ISOLATED INTEGRATED CIRCUITS [J].
MURPHY, BT ;
GLINSKI, VJ ;
GARY, PA ;
PEDERSEN, RA .
PROCEEDINGS OF THE IEEE, 1969, 57 (09) :1523-+
[9]  
SZE SM, 1969, PHYSICS SEMICONDUCTO, P214
[10]  
SZE SM, 1969, PHYSICS SEMICONDUCTO, P89