5-GBIT/S SI INTEGRATED REGENERATIVE DEMULTIPLEXER AND DECISION CIRCUIT

被引：9

作者：

CLAWIN, D

LANGMANN, U

SCHREIBER, HU

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1987年 / 22卷 / 03期

关键词：

D O I：

10.1109/JSSC.1987.1052736

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：385 / 389

页数：5

共 8 条

[1]

Clawin D., 1985, 1985 IEEE International Solid-State Circuits Conference, 32nd ISSCC. Digest of Technical Papers (Cat. No. 85CH2122-0), P222

[2]

CLAWIN D, 1987, IEEE J LT, V5, P348

[3]

CLAWIN D, 1986, 1986 P EUR SOL STAT, P158

[4] 4-GBIT/S TRANSMISSION OVER 103 KM OF OPTICAL FIBER USING A NOVEL ELECTRONIC MULTIPLEXER DEMULTIPLEXER [J].

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[5] 8 GBIT/S TRANSMISSION OVER 30-KM OF OPTICAL FIBER [J].

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CAMPBELL, JC .

ELECTRONICS LETTERS, 1986, 22 (11) :600-602

[6] A 4-1 TIME-DIVISION MULTIPLEXER IC FOR BIT RATES UP TO 6 GBIT/S BASED ON A STANDARD BIPOLAR TECHNOLOGY [J].

REIMANN, R ;

REIN, HM .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (05) :785-789

[7] A BIPOLAR MONOLITHIC MULTIGIGABIT/S DECISION CIRCUIT [J].

SUZUKI, M ;

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ICHINO, H ;

KONAKA, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (04) :462-467

[8] MONOLITHIC INTEGRATED 4-1 MULTIPLEXER AND DEMULTIPLEXER OPERATING UP TO 4-8 GBIT/S [J].

YOSHIKAI, N ;

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ELECTRONICS LETTERS, 1985, 21 (04) :149-151

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