PLANARIZATION OF DIELECTRICS USED IN THE MANUFACTURE OF VERY-LARGE-SCALE INTEGRATED-CIRCUITS

Dielectrics are used extensively for interlevel insulation in very-large-scale integrated circuits. The planarization of dielectrics has been investigated on single-crystal silicon substrates on which integrated circuits are built. Polysilicon gate of interconnect produces a step of about 0.5-mu-m which is covered with silicon dioxide (SiO2) to provide insulation. The vertical walls produced by the steps must be made less steep in order to achieve conformal step coverage of a metal film that is deposited on top of this glass. The reduction in the step incline is achieved by reflowing glass that has been made less viscous with dopants such as phosphorus and boron at low temperatures (600-1000-degrees-C). Several planarization steps have been examined, including ion implantation, bias sputtering and spin-on glass. Steam was found to be the best ambient, followed by oxygen and nitrogen.