We describe plans for a parallel computer composed of 16K nodes interconnected in a 16(3) x 4 mesh. Each node is made up of a Texas Instruments TMS320C31 digital signal processor, 0.5M words of error-corrected memory and a gate array providing memory management and inter-node communication. The machine will have a peak speed of 0.8Tflops and is estimated to sustain almost-equal-to 0.5Tflops for lattices as small as 32(3) x 8. We plan to complete the machine within two years for a cost of $3M.