A 2ND LEVEL DATA BUFFER WITH LHC PERFORMANCE

被引:4
作者
GREEN, BJ [1 ]
STRONG, JA [1 ]
CRANFIELD, R [1 ]
CRONE, G [1 ]
机构
[1] UCL, DEPT PHYS & ASTRON, LONDON, ENGLAND
关键词
D O I
10.1016/0168-9002(95)00107-7
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
For the ATLAS experiment at the Large Hadron Collider (LHC) buffers are required which will accept data at rates in excess of 100 Mbytes/s and distribute selected data to the second and third level trigger systems. A design for a buffer using a digital signal processor as the memory manager is described and the performance of a prototype module is given. Tests of the system in a beam line will be used to develop and check discrete event simulation models of the buffers and a second level trigger system.
引用
收藏
页码:359 / 362
页数:4
相关论文
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