OPTICAL RECEIVER ARRAY IN SILICON BIPOLAR TECHNOLOGY WITH SELFALIGNED, LOW PARASITIC III/V DETECTORS FOR DC-1 GBIT/S PARALLEL LINKS

被引：25

作者：

WIELAND, J ^{[1
]}

MELCHIOR, H ^{[1
]}

KEARLEY, MQ ^{[1
]}

MORRIS, CR ^{[1
]}

MOSELEY, AM ^{[1
]}

GOODWIN, MJ ^{[1
]}

GOODFELLOW, RC ^{[1
]}

机构：

[1] GEC MARCONI MAT TECHNOL,TOWCESTER NN12 8EQ,NORTHANTS,ENGLAND

来源：

ELECTRONICS LETTERS | 1991年 / 27卷 / 24期

关键词：

OPTICAL RECEIVERS; INTEGRATED OPTICS;

D O I：

10.1049/el:19911368

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 1 x 8 element III-V photodetector/silicon bipolar circuit receiver array has been fabricated using a selfaligning, low parasitic, flipchip solder bond hybridisation process. Receiver elements operate at data rates up to 1 Gbit/s with an input sensitivity of -23 dBm at 1.3-mu-m wavelength, and with negligible interchannel crosstalk. An overall delay of 1.5 ns was measured between optical input and digital output.

引用

页码：2211 / 2213

页数：3