A GAAS 4-QUADRANT ANALOG MULTIPLIER CIRCUIT

被引：1

作者：

SIFERD, R

机构：

[1] Department of Electrical Engineering, Wright State University, Dayton, OH

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1993年 / 28卷 / 03期

关键词：

D O I：

10.1109/4.210009

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A design for a four-quadrant analog multiplier is presented using GaAs MESFET transistors. The fabricated circuit has a -3-dB bandwidth of 410 MHz with 50-OMEGA/6.5-pF output loading, nonlinearity of less than 1%, and static power dissipation of 86.1 mW with V(dd) = 3 V and V(ss) = -2 V. Simulations indicate the circuit will operate at frequencies over 2.0 GHz with on chip loads of 0.15 pF.

引用

页码：388 / 391

页数：4

共 5 条

[1] A CMOS 4-QUADRANT ANALOG MULTIPLIER [J].