A 10-B 20-MSAMPLE/S ANALOG-TO-DIGITAL CONVERTER

被引：268

作者：

LEWIS, SH ^{[1
]}

FETTERMAN, HS ^{[1
]}

GROSS, GF ^{[1
]}

RAMACHANDRAN, R ^{[1
]}

VISWANATHAN, TR ^{[1
]}

机构：

[1] AT&T BELL LABS,ALLENTOWN,PA 18103

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 03期

关键词：

D O I：

10.1109/4.121557

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu-m CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm2 and dissipates 240 mW.

引用

页码：351 / 358

页数：8

共 26 条

[1] HIGH-FREQUENCY CMOS SWITCHED-CAPACITOR FILTERS FOR COMMUNICATIONS APPLICATION [J].