TEST-GENERATION FOR CURRENT TESTING

Current testing is useful for testing CMOS ICs because it can detect a large class of manufacturing defects, including defects that traditional stuck-at fault testing misses. The effectiveness of current testing can be enhanced if built-in current sensors are applied on chip to monitor defect-related abnormal currents in the power supply buses. Such sensors have proved effective for built-in self-test. However, current testing requires the use of a special method to generate test vectors. The authors describe this method, which differs from that for traditional voltage-oriented testing, and postulate a new test-generation algorithm for both on-chip and off-chip current testing. The algorithm uses realistic fault models extracted directly from the circuit layout. © 1990 IEEE