THE ARCHITECTURE OF A HIGH-PERFORMANCE MASS STORE WITH GMR MEMORY CELLS

被引：14

作者：

POHM, AV

DAUGHTON, JM

BROWN, J

BEECH, R

机构：

[1] Nonvolatile Electronics, Eden Prairie, MN 55344

来源：

IEEE TRANSACTIONS ON MAGNETICS | 1995年 / 31卷 / 06期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/20.490327

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high output, GMR, sub-micron memory cell has been designed for a 16 Mega-bit die with an area of 0.9 square cm. Using die parameters, a study was made of a wafer scale, high performance memory system with on board cache units. The study shows that gigabyte per second throughputs can be achieved while using modest power.

引用

页码：3200 / 3202

页数：3

共 5 条

[1] 1-MB MEMORY CHIP USING GIANT MAGNETORESISTIVE MEMORY CELLS [J].