BIT-SERIAL MULTIPLIERS AND SQUARERS

被引:23
作者
IENNE, P
VIREDAZ, MA
机构
[1] Swiss Federal Institute of Technology, Mantra Centre for Neuro-Mimetic Systems
关键词
D O I
10.1109/12.338107
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Traditional bit serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus goad candidates for introduction in VLSI libraries.
引用
收藏
页码:1445 / 1450
页数:6
相关论文
共 13 条
[1]  
CHEN TC, 1971, IEEE T COMPUT, VC 20, P678, DOI 10.1109/T-C.1971.223325
[2]   ON SERIAL-INPUT MULTIPLIERS FOR 2S COMPLEMENT NUMBERS [J].
DADDA, L .
IEEE TRANSACTIONS ON COMPUTERS, 1989, 38 (09) :1341-1345
[3]  
DADDA L, 1985, 7TH IEEE COMP AR, P57
[4]  
DADDA L, 1985, 7TH IEEE S COMP AR, P173
[5]  
GNANASEKARAN R, 1983, IEEE T COMPUT, V32, P878, DOI 10.1109/TC.1983.1676341
[6]  
IENNE P, 1993, OCT P INT C APPL SPE, P345
[7]  
IENNE P, 1992, 927 EC POL FED LAUS
[8]   2S COMPLEMENT PIPELINE MULTIPLIERS [J].
LYON, RF .
IEEE TRANSACTIONS ON COMMUNICATIONS, 1976, 24 (04) :418-425
[9]  
RHYNE T, 1986, IEEE T COMPUT, V35, P896, DOI 10.1109/TC.1986.1676680
[10]  
SIPS HJ, 1982, IEEE T COMPUT, V31, P325, DOI 10.1109/TC.1982.1676000