LOGIC GATES WITH SHAPED JOSEPHSON JUNCTIONS

被引:11
作者
MOSER, A
机构
[1] IBM Zurich Research Laboratory, Rüschlikon Switzerland
关键词
D O I
10.1109/JSSC.1979.1051243
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Long (L/λj> 5) in-line Josephson junctions, with varying width along the length L of the device, are investigated as logic gates (‘Aj being the Josephson penetration depth). The devices realized have an asymmetric threshold characteristic with almost suppressed side-lobes, providing good logic gain and permitting logic fan-in with multiple control 1ines. Optimum conditions are found for junctions with width varying approximately sinusoidally along the device length. The so-called shaped junctions are incorporated in various flip-flop circuits to evaluate the transfer time and transfer efficiency of loop circuits, and in a self-resetting inverter circuit to demonstrate the feasibility of self-resetting logic. The principle of current steering and the relatively large operating currents (I G z: 6 mA) make the circuits suitable for medium-speed applications such as in the decode and control logic of a main-memory chip. For a fan-out of four, the minimum circuit delay is 300 ps, resulting in a power-delay product in the order of 3.10–15 J. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.
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收藏
页码:672 / 679
页数:8
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