IMPLEMENTATION OF A LEARNING KOHONEN NEURON BASED ON A NEW MULTILEVEL STORAGE TECHNIQUE

This paper describes a compact implementation of a fully parallel Kohonen network with learning capabilities. Implementation issues concerning general neural networks are briefly explored, and an original mixed analog and digital technique to store discrete voltages on a capacitor is presented. The limitations are discussed and measurements on the storage dynamics are reported, which show that 8 b of resolution are achievable. This technique is applied to the realization of a neuron dedicated to Kohonen maps. This neuron has been implemented in a standard 2-mu-m CMOS technology, and the synaptic functions are very dense.