TIMING ANALYSIS AND PERFORMANCE IMPROVEMENT OF MOS VLSI DESIGNS

被引：41

作者：

JOUPPI, NP ^{[1
]}

机构：

[1] STANFORD UNIV,COMP SYST LAB,STANFORD,CA 94305

来源：

关键词：

D O I：

10.1109/TCAD.1987.1270311

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：650 / 665

页数：16

共 26 条

[1]

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[2]

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[3]

CLARK JH, P SIGGRAPH 82

[4]

DEGEUS AJ, 1984, 21ST P IEEE DES AUT, P536

[5]

FODERARO JK, 1982, VLSI DES, V3, P27

[6]

HENNESSY J, 1981, OCT P CMU C VLSI SYS, P337

[7]

Hennessy J. L., 1983, Third Caltech Conference on Very Large Scale Integration, P33

[8] TIMING ANALYSIS OF COMPUTER HARDWARE [J].

HITCHCOCK, RB ;

SMITH, GL ;

CHENG, DD .

[9]

HITCHCOCK RB, 1982, 19TH P DES AUT C, P594

[10] DERIVATION OF SIGNAL FLOW DIRECTION IN MOS VLSI [J].

JOUPPI, NP .