IMPLEMENTATION OF THE POWERPC-601 MICROPROCESSOR

被引：3

作者：

BRODNAX, TB ^{[1
]}

BILLINGS, RV ^{[1
]}

GLENN, SC ^{[1
]}

PATEL, PT ^{[1
]}

机构：

[1] IBM CORP,RISC SYST 6000 DIV,AUSTIN,TX 78758

来源：

IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 1994年 / 38卷 / 05期

关键词：

D O I：

10.1147/rd.385.0621

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

To produce a marketable PowerPC(TM) microprocessor on a short development schedule, the logic had to be designed in a manner flexible enough to allow quick modifications without sacrificing high performance and density when customized cells were required. This was accomplished for the PowerPC 601(TM) microprocessor (601) with a high-level design-language description, which was synthesized for a gate-level implementation and simulated for functional verification. In a similar way, the physical design strategy for the 601 struck an attractive balance between a highly automated, flexible floorplan and the additional density that had to be available for limited, well-conceived manual placements. Finally, a rigorous test strategy was implemented, which has proved very useful in analyzing the processor and in assembling 601-based systems. Careful adherence to this methodology led to a successful first-pass physical implementation, leaving the second iteration for additional customer requests.

引用

页码：621 / 632

页数：12