A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

被引：33

作者：

BARTOLONI, A

BASTIANELLO, G

BATTISTA, C

CABASINO, S

MARZANO, F

PAOLUCCI, PS

PECH, J

RAPUANO, F

PANIZZI, E

SARNO, R

TODESCO, GM

TORELLI, M

TROSS, W

VICINI, P

CABIBBO, N

FUCCI, A

TRIPICCIONE, R

机构：

[1] UNIV ROMA TOR VERGATA,DIPARTIMENTO FIS,I-00173 ROME,ITALY

[2] INFN,SEZ ROMA 2,I-00173 ROME,ITALY

[3] CERN,CH-1211 GENEVA 23,SWITZERLAND

[4] UNIV PISA,DIPARTIMENTO FIS,I-56010 PISA,ITALY

[5] INFN,SEZ PISA,I-56010 PISA,ITALY

来源：

INTERNATIONAL JOURNAL OF MODERN PHYSICS C-PHYSICS AND COMPUTERS | 1993年 / 4卷 / 05期

关键词：

D O I：

10.1142/S0129183193000744

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.

引用

页码：969 / 976

页数：8

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