FAST CMOS ECL RECEIVERS WITH 100-MV WORST-CASE SENSITIVITY

被引:28
作者
CHAPPELL, BA
CHAPPELL, TI
SCHUSTER, SE
SEGMULLER, HM
ALLAN, JW
FRANCH, RL
RESTLE, PJ
机构
关键词
D O I
10.1109/4.257
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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引用
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页码:59 / 67
页数:9
相关论文
共 11 条
[1]   ELECTRICAL DESIGN OF A HIGH-SPEED COMPUTER PACKAGE [J].
DAVIDSON, EE .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1982, 26 (03) :349-361
[2]  
FLANNAGAN S, 1986, FEB ISSCC, P208
[3]   MOS OPERATIONAL-AMPLIFIER DESIGN - A TUTORIAL OVERVIEW [J].
GRAY, PR ;
MEYER, RG .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (06) :969-982
[4]  
HUDSON E, 1982, FEB ISSCC, V25, P248
[5]  
LAI F, 1985, IEEE J SOLID STATE C, V20, P123
[6]  
OHMORI Y, 1985, 17TH C SOL STAT DEV, P53
[7]  
OHTANI T, 1987, FEB ISSCC, P264
[8]  
SCHUSTER S, 1986, FEB ISSCC, P206
[9]  
Schuster S. E., 1985, 1985 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers, P24
[10]  
WANG K, 1987, FEB ISSCC, P254