PARALLEL AND PIPELINE ARCHITECTURES FOR 2-D BLOCK PROCESSING

被引：5

作者：

AZIMISADJADI, MR

ROSTAMPOUR, AR

机构：

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS | 1989年 / 36卷 / 03期

关键词：

D O I：

10.1109/31.17593

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：443 / 448

页数：6

共 9 条

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