A SYSTOLIC ARCHITECTURE FOR ITERATIVE LQ OPTIMIZATION

An efficient square root algorithm and its systolic implementation for LQ dynamic output regulation of a SISO plant are presented. Due to the particularity of the undertaken formulation, based on an input-output plant description, the problem under consideration exhibits a very special structure which is fully exploited by the proposed implementation. As compared to the best parallel LQ implementations conceived for generic state-space descriptions and cost-functionals, which use O(n2) processors and take O(n) processing time per iteration, our implementation uses a trapezoidal array of d(4n + 2d - 1) processors and takes O(n/d) time, where n is the plant order and d is a design parameter trading off computing speed versus hardware complexity. In particular, if d is O(n), processing time turns out to be independent of n. The proposed architecture, being capable of providing the optimal feedback gain both in "receding horizon" and "iterations spread in time" modes, could be profitably used to speed up the controller parameter synthesis task in an adaptive control environment for applications where both high speed and high performance are demanded.