BOTTOM-OXIDE SCALING FOR THIN NITRIDE OXIDE INTERPOLY DIELECTRIC IN STACKED-GATE NONVOLATILE MEMORY CELLS

被引：10

作者：

MORI, S ^{[1
]}

SAKAGAMI, E ^{[1
]}

KANEKO, Y ^{[1
]}

OHSHIMA, Y ^{[1
]}

ARAI, N ^{[1
]}

YOSHIKAWA, K ^{[1
]}

机构：

[1] TOSHIBA MICROELECTR CORP,SAIWAI KU,KAWASAKI 210,JAPAN

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1992年 / 39卷 / 02期

关键词：

D O I：

10.1109/16.121684

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents novel results concerning thin Nitride-Oxide (NO) interpoly dielectric in nonvolatile memories. Optimized NO films with a thick top oxide and a thin nitride structure offers sufficient charge retention capability in the 12-nm effective oxide thickness region. However, this structure shows an anomalous threshold voltage increase due to the back tunneling of electrons from the NO film to a floating gate. Such electrons can be injected into the NO film during programming and baking. The magnitude of this voltage depends on the NO film structure and the electric field during the program or bake procedure. Therefore, these phenomena must be taken into consideration in designing the cell structure and its operating conditions. The results obtained in this study are also useful when considering ONO (Oxide-Nitride-Oxide) scaling in the thin bottom-oxide region for nonvolatile memory applications.

引用

页码：283 / 291

页数：9

共 17 条

[1] FAST PROGRAMMABLE 256K READ ONLY MEMORY WITH ON-CHIP TEST CIRCUITS [J].

ATSUMI, S ;

TANAKA, S ;

SHINADA, K ;

YOSHIKAWA, K ;

MAKITA, K ;

NAGAKUBO, Y ;

KANZAKI, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (01) :422-427

[2]

BAGLEE DA, 1990, 1990 P IEEE IRPS, P12

[3]

Bergemont A., 1989, International Electron Devices Meeting 1989. Technical Digest (Cat. No.89CH2637-7), P591, DOI 10.1109/IEDM.1989.74350

[4] A 68-NS 4-MBIT CMOS EPROM WITH HIGH-NOISE-IMMUNITY DESIGN [J].

IMAMIYA, K ;

MIYAMOTO, J ;

ATSUMI, S ;

OHTSUKA, N ;

MUROYA, Y ;

SAKO, T ;

HIGASHINO, M ;

IYAMA, Y ;

MORI, S ;

OHSHIMA, Y ;

ARAKI, H ;

KANEKO, Y ;

NARITA, K ;

ARAI, N ;

YOSHIKAWA, K ;

TANAKA, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (01) :72-78

[5] AN ERASE MODEL FOR FAMOS EPROM DEVICES [J].

KATZNELSON, RD ;

FROHMANBENTCHKOWSKY, D .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (09) :1744-1752

[6]

LIOU FT, 1984, IEEE T ELECTRON DEV, V31, P1736, DOI 10.1109/T-ED.1984.21780

[7]

MIELKE NR, 1983, 1983 P IEE IRPS, P106

[8] ONO INTER-POLY DIELECTRIC SCALING FOR NONVOLATILE MEMORY APPLICATIONS [J].

MORI, S ;

SAKAGAMI, E ;

ARAKI, H ;

KANEKO, Y ;

NARITA, K ;

OHSHIMA, Y ;

ARAI, N ;

YOSHIKAWA, K .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (02) :386-391

[9]

MORI S, 1989, AUG IEEE NVSMW VAIL

[10]

OHJI Y, 1987, 1987 IEEE P INT REL, P55

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