A MINIMIZATION TECHNIQUE FOR MULTIPLE-VALUED LOGIC SYSTEMS

被引:69
作者
ALLEN, CM
GIVONE, DD
机构
关键词
D O I
10.1109/TC.1968.227407
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
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页码:182 / +
页数:1
相关论文
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  • [3] Berlin R.D., 1958, IEEE T ELECT COMPUT, V7, P52
  • [4] LOWENSCHUSS O, 1958, IRE NAT CONV REC 4, V1, P305
  • [5] LOGICAL DESIGN OF TERNARY SWITCHING CIRCUITS
    YOELI, M
    ROSENFELD, G
    [J]. IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1965, EC14 (01): : 19 - +