AN ALPHA-IMMUNE, 2-V SUPPLY VOLTAGE SRAM USING A POLYSILICON PMOS LOAD CELL

被引:10
作者
ISHIBASHI, K
YAMANAKA, T
SHIMOHIGASHI, K
机构
[1] Central Research Laboratory, Hitachi Ltd., Kokubunji-shi, Tokyo, 185
关键词
D O I
10.1109/4.50284
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
- A SRAM for a supply voltage of as low as 2 V is investigated for realizing high-density SRAM’s using deep submicrometer devices. The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5-μm CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is comparable to that of the conventional high-resistivity polysilicon load cell at a supply voltage of 5 V. The cell stability is also improved using a PPL cell, so that the low-voltage operation is assured. © 1990 IEEE
引用
收藏
页码:55 / 60
页数:6
相关论文
共 7 条
[1]   STABILITY AND SER ANALYSIS OF STATIC RAM CELLS [J].
CHAPPELL, B ;
SCHUSTER, SE ;
SAIHALASZ, GA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (01) :383-390
[2]  
List F. J., 1986, SEP ESSCIRC, P16
[3]   WORST-CASE STATIC NOISE MARGIN CRITERIA FOR LOGIC-CIRCUITS AND THEIR MATHEMATICAL EQUIVALENCE [J].
LOHSTROH, J ;
SEEVINCK, E ;
DEGROOT, J .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (06) :803-807
[4]  
MINATO O, 1987, FEB ISSCC, P260
[5]  
MURAKAMI S, 1988, AUG S VLSI CIRC, P57
[6]  
TOYABE T, 1982, IEEE T ELECTRON DEV, V29, P732, DOI 10.1109/T-ED.1982.20770
[7]  
YAMANAKA Y, 1988, DEC IEDM, P48