共 10 条
[1]
Nakagawa, Impact of Dielectric Isolation Technology on Power IC's, ISPSD-91, pp. 16-21, (1991)
[2]
Mille, A very High Voltage Technology (up to 1200 V) for Vertical Smart Power IC's, Symposium on High Voltage and Smart Power ICs, pp. 517-521, (1989)
[3]
Appels, Vaes, High Voltage Thin Layer Devices (RESURF Devices), proc. IEDM, 35, pp. 238-241, (1979)
[4]
Charitat, Nezar, Rossel, Bidimensional Analysis of High Voltage RESURF LDMOS for Smart Power Integrated Circuits: On and Off State, Symposium on High Voltage and Smart Power ICs, pp. 11-20, (1989)
[5]
Charitat, Modélisation et réalisation de composants planar haute-tension, Thèse de doctorat d'état es sciences, (1990)
[6]
Charitat, Jaume, Peyre-Lavigne, Rossel, 1000 and 1500 volts Planar Devices using Field Plate and Semi-Resistive Layers: Design and Fabrication, proc. IEDM, pp. 803-806, (1990)
[7]
Jaume, Charitat, Reynes, Possel, High-Voltage Planar Devices Using Field Plate and Semi-Resistive Layers, IEEE Trans. Elec. Dev., 38 ED, 7, pp. 1681-1684, (1991)
[8]
Van Overstraten, Deman, Measurement of the ionization rates in diffused silicon p-n junction, Solid-State Electron., 13, (1970)
[9]
Mukherjee, Chou, Saw, McArthur, Rummenik, The Effects of Sipos Passivation and DC Swotching Performance of High Voltage MOS Transistors, proc. IEDM, pp. 646-649, (1986)
[10]
Taylor, Tong, Density of States at the Interface between Semi-Insulating Polycristalline and Single Cruystal Silicon, J. Appl. Phys., 56, 6, pp. 1881-1883, (1984)