SORTING NETWORK-BASED ARCHITECTURES FOR MEDIAN FILTERS

被引：25

作者：

CHAKRABARTI, C

机构：

[1] Department of Electrical Engineering, Center for Telecommunications Research, Arizona State University, Tempe

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1993年 / 40卷 / 11期

关键词：

D O I：

10.1109/82.251840

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Sorting network based architectures for computing nonrecursive and recursive median filters are presented. The proposed architectures are highly pipelined and consist of fewer compare-swap units than existing architectures. The reduction in the number of compare-swap units is achieved by minimizing computational overlap between successive outputs and also by using Batcher's odd-even merge sort (instead of bubble-sort). The latency of these networks is reduced by building them with sorting units that sort 2 elements (sort-2) as well as 3 elements (sort-3) in 1 time unit.

引用

页码：723 / 727

页数：5

共 12 条

[1]

ARCE GR, 1984, 22ND P ANN ALL C COM, P172

[2]

BATCHER KE, 1968 SPR JOINT COMP, V32, P307

[3]

BONCELET CG, 1988, P IEEE INT C CIRCUIT, P1745

[4]

CHAKRABARTI C, 1992, P IEEE INT C CIRCUIT

[5]

CHAKRABARTI C, IEEE T SIGNAL PR MAR

[6]

FISHER AL, 1982, J DIGITAL SYST, V4, P251

[7]

HWANG JN, 1990, PROCEEDINGS OF THE INTERNATIONAL CONF ON APPLICATION SPECIFIC ARRAY PROCESSORS, P90, DOI 10.1109/ASAP.1990.145446

[8]

Karaman M., 1988, VLSI SIGNAL PROCESSI, VIII, P111

[9]

KUNG SY, 1989, VLSI ARRAY PROCESSOR

[10]

LUCKE L, 1992, P IEEE INT C CIRCUIT

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