A high speed wide range pipelined integrator and encoder ASIC for fast digitization of charge from photomultiplier tubes is under development at Fermilab. The ASIC is intended to operate in conjunction with a FADC to digitize signals from a charge source over a dynamic range of 18-20 bits with 8-10 bits of accuracy every 16 ns. Development of the device called QIE (charge integrator and encoder) is being carried out in an IC process with CMOS and NPN devices. Many chips have been designed and tested to prove the feasibility of the device.
