VLSI Architecture for Block-Matching Motion Estimation Algorithm

被引：130

作者：

Hsieh, Chaur-Heh ^{[1
]}

Lin, Ting-Pang ^{[1
]}

机构：

[1] Natl Chung Cheng Univ, Dept Elect Engn, Tao Yuan, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | 1992年 / 2卷 / 02期

关键词：

D O I：

10.1109/76.143416

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The block-matching motion estimation Is the most popular method for motion-compensated coding of image sequence. This paper presents a VLSI architecture for Implementing a full-search block-matching algorithm. Based on a systolic army processor and shift register arrays with programmable length, the proposed architecture has the following advantages: 1) it allows serial data Inputs to save the pin counts but performs parallel processing, 2) It Is flexible In adaptation to the dimensional change of the search am via simple control, 3) It can operate in real time for videoconference applications, and 4) it Is simple and modular in design and thus is suitable for VLSI implementation.

引用

页码：169 / 175

页数：7

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