300 V-MU-S MONOLITHIC VOLTAGE FOLLOWER

被引:3
作者
ERDI, G
机构
[1] Precision Monolithics, Inc., Santa Clara
关键词
D O I
10.1109/JSSC.1979.1051315
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An open-loop, JFET input, high-speed buffer, designed without feedback, is described. Careful biasing of source and emitter followers ensures accurate unity gain and gain linearity with 10 mA of load current. A unique quasi-quad input PET layout provides excellent matching and thermal gradient cancellation and simultaneously optimizes speed performance. Offset voltage is permanently adjusted at wafer test by Zener-zap trimming. The output is capable of driving large capacitive loads with 70 mA of peak current. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.
引用
收藏
页码:1059 / 1065
页数:7
相关论文
共 4 条
[1]   PRECISION TRIM TECHNIQUE FOR MONOLITHIC ANALOG CIRCUITS [J].
ERDI, G .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, 10 (06) :412-416
[2]  
ERDI G, 1969, 136 FAIRCH SEM APPL
[3]  
RUSSEL RW, 1974, FEB ISSCC, P140
[4]  
SOLOMON JE, 1974, IEEE J SOLID STATE C, V9, P322